1. Field of the Invention
The present invention relates to a method for fabricating a nonvolatile memory cell, and more especially, to a method for fabricating textured tunnel oxide with high electron injection efficiency and a large charge-to-breakdown for low power nonvolatile memory.
2. Description of the Prior Art
Nonvolatile memories, including mask read-only memories (Mask ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM or E.sup.2 PROM) and flash memories, retain their memory data whenever the power is turned off, and have wide applications in the computer and electronic industry. In recent years, the portable computers and telecommunications market develop rapidly and become a major driving force in semiconductor integrated circuit's design and technology. As stated by A. Bergemont, et al., in "Low Voltage NVG.TM.: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Application", IEEE Trans. Electron Devices Vol. 43, p. 1510, (1996), it creates a great need for low power, high density, and electrically re-writable nonvolatile memories. That is, the memories programmable and erasable as EPROM, E.sup.2 PROM or flash memories are required for aforementioned systems to store operating systems or applications software.
The basic storage cell of these programmable and erasable memories contain a double polysilicon storage transistor with a floating gate isolated in silicon dioxide and capacitively coupled to a second control gate which is stacked above it. The E.sup.2 PROM cell further comprises an access, or select, transistor. These memories execute the program and erasure by charging or discharging their floating gates. For example, the EPROM is programmed by hot electron injection at the drain to selectively charge the floating gate and erased by discharging the floating gate with ultraviolet light or X-ray, which the latter has never been commercially applied for this purpose. The E.sup.2 PROM and most of the flash memories are programmed by hot electron injection or cold electron tunneling named Flower-Nordheim tunneling, and erased mostly by Flower-Nordheim tunneling from the floating gate to the source, with the control gate ground.
Flower-Nordheim tunneling, or cold electron tunneling, is a quantum-mechanical effect, which allows the electrons to pass through the energy barrier at the silicon-silicon dioxide interface at a lower energy than required to pass over it. H. Shirai, et al., stated in their paper "A 0.54 .mu.m.sup.2 Self-Aligned, HSG Floating Gate Cell (SAHF Cell) for 256 Mbit Flash Memories", IEDM Tech. Dig. Vol. 95, p. 653, (1995) that, because of its low current consumption, the Flower-Nordheim program/erase scheme becomes indispensable for low power operation of the E.sup.2 PROM and flash memories. But the Flower-Nordheim program/erase scheme requires high voltage that applied to control gate of the memory cell due to its need for a large reversible electric field to the thin oxide separating the floating gate from the substrate. Therefore, to lower the control gate bias, the memory cell must have a high capacitive-coupling ratio structure.
Y. S. Hisamune, et al., propose a method for fabricating a flash memory cell with contactless array and high capacitive-coupling ratio in "A High Capacitive-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories", IEDM Tech. Dig. Vol. 93, p. 19, (1993). But this method achieves high capacitive-coupling ratio with four times of polysilicon deposition and has a complex fabrication. In addition, this cell structure makes it difficult to scale the size down and increase the integration of the memory due to its short tunnel oxides. Furthermore, as mentioned by C. J. Hegarty, et al., in "Enhanced Conductivity and Breakdown of Oxides Grown on Heavily Implanted Substrates", Solid-State Electronics, Vol. 34, p. 1207, (1991). It is also difficult to fabricate a thin tunnel oxide on the heavily doped substrate with a high electron injection efficiency and a large charge-to-breakdown for low power nonvolatile memories. Thus, to reach high capacitive-coupling ratio, high electron injection efficiency and a large charge-to-breakdown with a simple manufacture is the subject of high density and low power nonvolatile memories today.